Data processing devices sometimes employ modules that are in different clock domains, with each domain synchronized to a clock that is asynchronous with the clocks of other clock domains. When data is transferred between clock domains, the data processing device employs a synchronization technique to ensure that the data is transferred properly. One method of transferring data between devices having different clock domains uses a First In First Out (FIFO) memory. Data to be transferred is written to the FIFO memory by a device in one clock domain (the source clock domain) and read from the FIFO by a device in the other clock domain (the target clock domain). One of the clock domains provides a pointer to the other clock domain indicating the FIFO memory location where the data has been written. The target clock domain does not read from the FIFO memory location until the pointer has been generated at one clock domain and provided to the other clock domain through a metastability synchronizer that allows the pointer to be reliably passed between the clock domains, ensuring that the data has been properly stored in the FIFO memory location before it is read. However, if the clock domain that receives the pointer is slower than the clock domain that generated the pointer, the amount of time required to reliably provide the pointer via the synchronizer is increased. This increased latency can cause an undesirable delay in communication of data between the clock domains, or require an undesirable increase in the size of the FIFO memory to accommodate data to be transferred. Accordingly, there is a need for an improved technique for transferring data between clock domains.